Another thought provoking article by Brian Bailey, Technology Editor/EDA for Semiconductor Engineering.

Optimization Challenges For 10nm And 7nm

“Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.”

“Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation.”

Read the full article:

https://semiengineering.com/optimization-challenges-for-10nm-and-7nm/

For more information about Moortec visit: www.moortec.com

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