With advances in CMOS technology and the scaling of transistor channel lengths to nanometer (nm) dimensions, the density of digital circuits per unit area of silicon has increased as has the process variability of devices manufactured.
The increase in digital logic (or gate) density, which equates to an increase in power density, is a major contributor to the heating of semiconductor devices manufactured on advanced node CMOS technologies. In-chip temperature monitoring is used for performance optimisation, an example being Dynamic Voltage and Frequency Scaling (DVFS) where, depending on the thermal conditions, system clocks and voltage supplies can be varied to optimise either the speed of logical operations or power consumed by the device.
Process induced variations in circuit delays have begun to significantly adversely affect chip performance and power consumption. A statistical analysis of each device would show a process variability, or spread, that when compared to historical CMOS technologies is wider (worse) for advanced technology nodes. To address this, manufacturers have to design their Systems-on-Chip (SoC) to over-compensate for unwanted variability arising from manufacturing processes.
Increased logic gate density, increased track and via impedances and process variability has led to significant voltage (IR) drops across advanced node devices. Together with an increasingly noisy environment, the need to monitor core supplies in-chip has become desirable to ensure that operating conditions are acceptable to the complex systems in today’s devices.
Designers of large, advanced node SoCs are grappling with two pressures: i) the desire for lower supplies, enabling compelling power performance for products, especially consumer technologies; and ii) jeopardising the functional operation of SoCs and an entire product range. The dilemma for the designer is that to maximise the former, optimisation schemes used today are algorithmically treading an increasingly thinner line between robust operation and having failing devices within the field. This is especially challenging when considering dynamic and static IR drop within complex devices. Through finer-grain and more responsive in-chip supply and voltage monitoring, the designer is able to develop higher performance optimisation schemes, whilst ensuring devices and hence product, remains operational within its application.
Moortec’s easy to integrate, embedded monitoring subsystem includes a high precision low power junction Temperature Sensor that has been developed to be embedded into ASIC designs. It can be used for a number of different applications including Dynamic Frequency and Voltage Scaling (DVFS), device lifetime enhancement, device characterisation and thermal profiling.
It also features a Process Monitor which provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices. The Process Monitor can be used to enable continuous DVFS optimisation systems, monitor manufacturing variability across chip, gate delay measurements, critical path analysis, critical voltage analysis and also monitor silicon ‘ageing’.
Lastly the Voltage Monitor is a low power self-contained IP block specially designed to monitor voltage levels within the core logic voltage domains and provide accurate IR drop analysis. The measurement range is customized to suit each technology. The monitor IP can also monitor analogue (IO) supply domains and is also well-suited to monitoring supply droops and perturbations.
The subsystem also includes the sophisticated Process, Voltage and Temperature (PVT) Controller with AMBA APB interfacing, which supports multiple monitor instances, statistics gathering, a production test access port as well as other compelling features.
Moortec’s PVT monitoring subsystem IP is designed to optimise performance in today’s cutting-edge technologies, solving the problems that come about through scaling of devices. Applications include Datacentre & Enterprise, Automotive, Mobile, IoT, Consumer and Telecommunications.
In-chip monitoring has become a vital factor in the design and performance optimisation of small-geometry designs. Since 2010 Moortec have brought to market a highly featured embedded PVT sensing fabric for or use in-chip within advanced node CMOS technologies from 40nm down to 7nm.
Established in 2005, Moortec (Plymouth, UK) provides compelling embedded subsystem IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 7nm. Moortec’s in-chip sensing solutions support the semiconductor design community’s demands for increased device reliability and enhanced performance optimization, enabling schemes such as DVFS, AVS and power management control systems. Moortec provides excellent support for IP application, integration and device test during production. Moortec’s high-performance analog and mixed-signal IP designs are delivered to ASIC and System on Chip (SoC) technologies within the consumer, mobile, automotive, high performance computing and telecommunications sectors. For more information please visit www.moortec.com, follow us on Twitter and LinkedIn.