The New Moortec Embedded Process Detector (MEPD) circuit provides the means for advanced node Integrated Circuit (IC) developers to detect the process variations brought about by manufacturing variability and drift of advanced node core digital MOS devices. The Process Detector can be used to enable a continuous Dynamic Voltage & Frequency Scaling (DVFS) optimisation system, monitor manufacturing variations on and if required, across chip, gate delay measurements, critical path analysis, critical voltage analysis and also monitor silicon ‘ageing’.

Moortec Semiconductor Limited, provider of mixed-signal IP and custom chip solutions, believe that on-chip Process, Voltage and Temperature (PVT) monitoring has become a vital factor in the design and performance optimisation of small-geometry designs. Moortec, which provides high performance analogue IP to customers world-wide, produces process, voltage and temperature (PVT) monitoring and optimization IP for CMOS geometries such as 40-nanometer (nm), 28-nm and FinFET. 

Using such
monitors embedded within System on Chip (SoC) designs allows for greater dynamic
performance optimization as sensing die temperature, detecting logic speed and
monitoring voltage supply levels can be used intelligently to vary system clock
frequencies and the voltage levels of supply domains. 

A key aspect is
that optimisation can be applied to each and every device, either during
production or when devices are ‘in-the-field’. Moortec also believes that
strategies adopted by IC designers over the coming years will be heavily influenced
through the analysis of data harvested from in-chip monitors during the life
time of every device.

“The
greater process variability that is apparent at these challenging small
geometry CMOS technologies is forcing the IC design community to look at conditions
on-chip, not just generally but also per device and within regions of a
device,” said Stephen Crosher, Managing Director of Moortec Semiconductor.
“The industry faces the challenge posed by demand for increasingly integrated,
increasingly functional, giga-scale
ICs for applications such as personal mobile technology and multi-core server
configurations, whilst trying to improve battery life and maintaining optimal
performance. At low-geometry nodes, track and via resistances are dramatically
increasing, core supply headroom is diminishing and the power consumption per
unit area of silicon is increasing, whether that be through static leakage
current or dynamic current consumption. Our easily-to-integrate PVT monitoring
solutions are well placed to enable Dynamic Voltage and Frequency Scaling
(DVFS) optimisation schemes to be used within the designs.”

Moortec plan to
continue extending their IP range within the embedded monitoring space by
providing PVT subsystems, extended digital interfacing (eg. AMBA APB) and DVFS
sub-systems, making their technologies available on 28-nm and FinFET process
nodes.

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