As a new member of the TSMC IP Alliance, Moortec Semiconductor will be exhibiting at the TSMC 2015 Open Innovation Platform in Santa Clara, Calif. on Thursday 17th September. The event is taking place at the Santa Clara Convention Centre, so why not come and meet us at Booth #705 and discuss in person how your advanced node System on Chip (SoC) programme can benefit from Moortec’s high performance analog IP?

Specialising in embedded Process, Voltage and Temperature (PVT) sensors, Energy Optimisation Sub-systems (EOS) and Global Device Monitoring (GDM) for advanced nodes, Moortec’s IP enables SoC designs to be performance optimised and monitored on a per die basis.

Moortec specialises in the following IP solutions:

PVT Monitoring IP – ‘Lift the lid’ on conditions on-chip for performance optimisation and reliability. High accuracy on-chip thermal sensing, supply monitoring and process type discovery at 28nm and FinFET. For Dynamic Frequency and Voltage Scaling (DVFS), device life-time reliability, device characterisation and thermal profiling.

Energy Optimisation IP – Optimise device power consumption or optimise data throughput with Moortec’s EOS sub-system. Achieve by monitors sensing the device’s embedded conditions. Available for advanced nodes with AMBA APB, iJTAG, I2C and SPI interfacing.

Global Device Monitoring – Provision for deeper in-field monitoring.
For more information on this event please visit:

https://www.hwacomms.com/TSMC2015/OIP/Partner/index.php

To arrange a meeting with Moortec Semiconductor at this event to discuss your analogue IP requirements please contact:

ramsay.allen@moortec.com

About Moortec Semiconductor
Moortec Semiconductor, established in 2005, provides high quality analog and mixed-signal IP solutions world-wide for a variety of applications. Having a track record of delivery to tier-1 semiconductor and product companies, Moortec provides a quick and efficient path to market for customer products and innovations.

For information please visit:

www.moortec.com

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