If you are working on advanced node Data Center or AI chips you will be only too aware of design challenges such as CPU utilisation in the context of the device power consumed and the constraints to processing speed. Cutting-edge AI & Data Center Chips, by their advanced node nature, are susceptible to intra-die process variability. Designers are often also walking a fine line due to their desire to operate close to the edge of supply conditions.
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This latest webinar from Moortec looks at how optimising temperature and voltage supply and identifying process corners using embedded in-chip monitoring subsystems can greatly improve the power consumption, data throughput and computational performance of the overall system design.Topics covered in the webinar will include:
  • Thermal & voltage guard-banding
  • System energy consumption
  • Optimisation of multi-core utilisation
  • Optimising algorithmic computation & data throughput
  • Fine-grain DVFS/AVS control

Date & Time: Wednesday 27th of February at 6pm GMT (10am PST)

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